Voltage and current/voltage analog multipliers are currently used, e.g., to monitor power consumption in several applications involving “smart” architectures for evaluating and managing power consumption.
Such applications may involve computing power by multiplying values indicative of a voltage and a current supplied to a load.
Conventional analog voltage multipliers may comprise a combination of logarithmic and anti-logarithmic amplifiers.
Another conventional approach for implementing an analog multiplier may involve using a MOSFET transistor as a voltage-controlled resistor.
In comparison with arrangements including logarithmic amplifiers, a MOSFET implementation may be advantageous due to fewer devices involved and a simpler implementation. A MOSFET implementation may have an intrinsic limitation in being based on a linear approximation of the MOSFET characteristics.
While analog architectures are increasingly and almost completely replaced by digital architectures (e.g., digital integrated circuits or ICs) in certain applications conventional circuits based on logarithmic amplifiers are still currently resorted to in order to provide signal compression, for instance.
Such arrangements suffer from intrinsic drawbacks of analog circuits such as, e.g. errors due to gain inaccuracies, bias currents, offset effects, temperature dependency and non-linearity as possibly related to operational amplifier (op-amp) structures. Still other drawbacks may be related to complex calibration techniques and large silicon area occupancy.
Certain basic textbooks such as, e.g. Ramon Pallas-Areny, et al.: “Analog signal processing”, John Wiley & Sons, Inc. 1999, pp. 293-321 provide a comprehensive presentation of analog solutions as discussed in the foregoing.
There is a need in the art to provide improved solutions capable of facilitating signal multiplication by using an arrangement of reduced complexity with associated reductions in calibration time, cost and silicon area occupancy.